There is an increasing need for a semiconductor memory device capable of electrically erasing and programming without a refresh of a stored data. In addition, there is continual pressure to increase storage capacity and integration density of the memory device. A NAND type flash memory device is one example of a nonvolatile semiconductor memory device capable of providing a high capacity and high integration density without a refresh of stored data. Data is preserved even at power-off. The flash memory device is widely employed in electronic devices having a possibility that a power supply is interrupted suddenly (e.g., a portable terminal, a portable computer, etc.)
FIG. 1 is a block diagram illustrating a conventional NAND type flash memory device. Referring to FIG. 1, the NAND type flash memory device 10 includes a memory cell array 20, a row selection circuit (marked as “X-SEL” in the drawing) 40, and a sense and latch circuit 60 (alternatively called a page buffer circuit). A memory cell array 20 includes a plurality of cell strings (or NAND strings) 21 each string connected to one of bit lines BL0–BLm. The cell string 21 in each column comprises a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and a plurality of flash EEPROM cells MCn (n=0–15) connected in serial between the selection transistors SST and GST. The string selection transistor SST in each column includes a drain connected to a corresponding bit line and a gate connected to a string selection line SSL. The ground selection transistor GST includes a source connected to a common source line CSL and a gate connected to a ground selection line GSL. Flash EEPROM cells MC15–MC0 are connected in serial between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The cells in each cell string include floating gate transistors and the control gates of the transistors are connected to corresponding word lines WL15–WL0, respectively.
The string selection line SSL, the word lines WL0–WL15, and the ground selection line GSL are electrically connected to a row selection circuit 40 (X-SEL). The row selection circuit 40 selects one of the word lines according to row address information, and provides word line voltages to the selected word line and the non-selected word lines as determined by each operation mode. For example, the row selection circuit 40 provides a program voltage (e.g., 15V–20V) to a selected word line in a program mode, and a pass voltage (e.g., 10V) to non-selected word lines. The row selection circuit 40 provides a ground voltage (GND) to a selected word line and a read voltage (e.g., 4.5V) to non-selected word lines in a read mode. The program voltage, the pass voltage and the read voltage are higher than a power supply voltage. The bit lines BL0–BLm disposed through the memory cell array 20 are electrically connected to the sense and latch circuit 60. The sense and latch circuit 60 senses data from the flash EEPROM cells of the word line selected through the bit lines BL0–BLm in the read mode, and provides a power supply voltage (or a program-inhibited voltage) or a ground voltage (or a program voltage) to the bit lines BL0–BLm according to data to be programmed in a program mode.
In a NAND type flash memory device, the cells not to be programmed (referred to as a program-inhibited cell, hereinafter) may be soft-programmed by a program voltage due to characteristics of the cell structure as widely known. This is called a program disturbance. The program disturbance of the program-inhibited cell can be prevented by raising a channel voltage of the cell string to which the program-inhibited cell belongs, and this is called a self-boosting scheme. The channel voltage of the cell string follows a pass voltage provided to each of the non-selected word lines. As the pass voltage increases, soft-programming of the program-inhibited cell can be further suppressed. To the contrary, if the pass voltage increases, memory cells connected to each of the non-selected word lines may be soft-programmed by a pass voltage, and this is call “a pass disturbance”. Therefore, the pass voltage should be determined considering the above conditions.
Methods of restricting programming using the self-boosting scheme fully explained above are disclosed in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN”, and in U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURBANCE DURING SELF-BOOSTING IN A NAND FLASH MEMORY”, and incorporated herein by reference.
In case of the NAND type flash memory device, memory cells of one word line may be programmed at the same time. Alternatively, the memory cells in one word line are divided into some parts, and respective parts of the memory cells may be programmed individually. This is called “a partial program scheme”. In the former case, the memory cells in an identical word line are less affected by the program disturbance, while the memory cells in an identical word line are much affected by the program disturbance in the latter case. Assume that, for example, only the data to be programmed in the memory region of the bit lines BL0–Bli (a part marked with diagonal hash marks in FIG. 2) is loaded on the sense and latch circuit 60, as illustrated in FIG. 2. The memory cells in the region with a loaded data and the memory cells in the region without loaded data (in which bit lines BLi+1–BLm are arranged) are all connected to an identical word line, such that the program voltage is provided to the identical word line of the memory cells regardless of positions where the data loaded. Therefore, the possibility that the program-inhibited memory cell(s) is (are) soft-programmed increases as the number of the partial program (NOP) is rising.
This method of partial programming is often used to manage data in a small unit compared to a page size when the page size is large. For example, when using a device having a 2112 (2K+64)-sized page, four-times partial programs should be ensured for a user to perform a program by a unit of 528 (512+16) bytes. 16 bytes of the 528 bytes are stored in the spare field memory region (referring to FIG. 2), and 512 bytes are stored in the main field memory region.
Accordingly, if the number of times of partial program increases, the NAND type flash memory device becomes more susceptible to program disturbance.